1. Field of Invention
This invention relates to a semiconductor package module. More particularly, the present invention is related to a stacked package module.
2. Related Art
A well-known stacked package module employs a plurality of chips stacked with each other in a vertical direction so as to have the thickness of the package module smaller and smaller. As a package module disclosed in TW Pat. 527018, it illustrates that the external terminals, such as solder balls and leads, for connecting the packages with each other are disposed at the periphery of the carrier. It is easy to rework to reach the reliability requirement of package units, but the external terminals of the package units are not easy to align with each other so as to lower the reliability of the package module.
Moreover, another well-known package module as shown in FIG. 1 employs an intermediate substrate 30 formed between a first package 10 and a second package 20 to electrically connect the first package 10 and the second package 20 with each other. Therein, the second package 20 is located over the first package 10; the first package 10 has a chip 11 with bumps 12 formed thereon and a carrier 13 with solder balls 14 formed thereon wherein the chip 11 is attached to the carrier 13 through the bumps 12. To be noted, the intermediate substrate 30 has an opening 32 and a plurality of electrically conductive traces 31 formed therein to electrically connect the contacts 34, for electrically connecting the first package 10 and the second package 20, formed on the upper surface of the intermediate substrate 30 and the bumps 33 formed on the lower surface of the intermediate substrate 30. Because the size of the opening 32 shall be applicable to the size of the chip 11 for accommodating the chip 11 therein, the carrier 13 for carrying the chip 11 shall be designed upon the size of the chip 11, namely, the carrier 13 shall be designed according to the size of the opening 32. In addition, the intermediate substrate 30 has an opening 32 formed therein, accordingly, the stiffness of the intermediate substrate 30 becomes lower than that without opening formed therein so that such intermediate substrate 30 is easily to be warped. Hence, the bumps 21 and 33 are easily to be damaged due to the warpage of the intermediate substrate 30. On the basis, usually, the thickness and the warpage of the intermediate substrate 30 are required to be restricted to a limitation so as to prevent the bumps 21 and 33 from being damaged. This is the key and critical point to be resolved when such stacked package module is employed as an electronic component in an electronic application.
Therefore, providing another stacked package module to solve the mentioned-above disadvantages is the most important task in this invention.